{"id":269,"date":"2025-11-25T07:32:00","date_gmt":"2025-11-25T07:32:00","guid":{"rendered":"https:\/\/haco.club\/?p=269"},"modified":"2025-11-25T07:53:09","modified_gmt":"2025-11-25T07:53:09","slug":"aarch64-pre-post-indexing","status":"publish","type":"post","link":"https:\/\/haco.club\/?p=269","title":{"rendered":"AArch64 Pre\/Post Indexing"},"content":{"rendered":"\n

In AArch64 (ARMv8-A 64-bit architecture), Pre-indexing<\/strong> and Post-indexing<\/strong> are memory addressing modes used with Load (LDR<\/code>) and Store (STR<\/code>) instructions.<\/p>\n\n\n\n

Their primary purpose is to perform Writeback<\/strong>: they automatically update the base register (the pointer) with a new address as part of the instruction execution. This is extremely efficient for iterating through arrays or managing stacks because it eliminates the need for a separate ADD<\/code> or SUB<\/code> instruction to move the pointer.<\/p>\n\n\n\n

Here is the breakdown of how they work.<\/p>\n\n\n\n

\n\n\n\n

1. Pre-Indexed Addressing<\/h3>\n\n\n\n

Syntax:<\/strong> [base, #offset]!<\/code>
Key Symbol:<\/strong> The exclamation mark !<\/code> at the end.<\/p>\n\n\n\n

In pre-indexing, the offset is added to the base register before<\/strong> the memory access occurs. The base register is then permanently updated<\/strong> with this new address.<\/p>\n\n\n\n

Sequence of Operations:<\/strong><\/p>\n\n\n\n

    \n
  1. Calculate:<\/strong> Add the #offset<\/code> to the value in the base<\/code> register.<\/li>\n\n\n\n
  2. Update:<\/strong> Write this new value back into the base<\/code> register.<\/li>\n\n\n\n
  3. Access:<\/strong> Access memory using the new<\/strong> value.<\/li>\n<\/ol>\n\n\n\n

    Example:<\/strong><\/p>\n\n\n\n

    MOV X1, #0x1000     ; Set Base pointer (X1) to address 0x1000\nLDR X0, [X1, #8]!   ; Pre-indexed Load<\/code><\/pre>\n\n\n\n
      \n
    • Before:<\/strong> X1<\/code> = 0x1000<\/code><\/li>\n\n\n\n
    • Action:<\/strong> X1<\/code> becomes 0x1008<\/code> (0x1000 + 8). Memory is read from address 0x1008<\/code>.<\/li>\n\n\n\n
    • After:<\/strong> X0<\/code> holds the data from 0x1008<\/code>. X1<\/code> is now 0x1008<\/code>.<\/li>\n<\/ul>\n\n\n\n
      C Language Analogy:<\/strong>
      Similar to: data = *(ptr += 1);<\/code> (Increment pointer, then access).<\/p>\n\n\n\n
      \n\n\n\n
      2. Post-Indexed Addressing<\/h3>\n\n\n\n
      Syntax:<\/strong> [base], #offset<\/code>
      Key Visual:<\/strong> The offset is outside<\/strong> the square brackets.<\/p>\n\n\n\n
      In post-indexing, the memory access uses the current<\/strong> value of the base register. After<\/strong> the access is complete, the offset is added to the base register and the register is updated.<\/p>\n\n\n\n
      Sequence of Operations:<\/strong><\/p>\n\n\n\n
        \n
      1. Access:<\/strong> Access memory using the current<\/strong> value in the base<\/code> register.<\/li>\n\n\n\n
      2. Calculate:<\/strong> Add the #offset<\/code> to the base<\/code> register.<\/li>\n\n\n\n
      3. Update:<\/strong> Write this new value back into the base<\/code> register.<\/li>\n<\/ol>\n\n\n\n
        Example:<\/strong><\/p>\n\n\n\n
        MOV X1, #0x1000     ; Set Base pointer (X1) to address 0x1000\nLDR X0, [X1], #8    ; Post-indexed Load<\/code><\/pre>\n\n\n\n
          \n
        • Before:<\/strong> X1<\/code> = 0x1000<\/code><\/li>\n\n\n\n
        • Action:<\/strong> Memory is read from address 0x1000<\/code>. Then X1<\/code> becomes 0x1008<\/code>.<\/li>\n\n\n\n
        • After:<\/strong> X0<\/code> holds the data from 0x1000<\/code>. X1<\/code> is now 0x1008<\/code>.<\/li>\n<\/ul>\n\n\n\n
          C Language Analogy:<\/strong>
          Similar to: data = *ptr++;<\/code> (Access current pointer, then increment).<\/p>\n\n\n\n
          \n\n\n\n
          Summary Comparison<\/h3>\n\n\n\n
          To visualize the difference, assume X1<\/code> starts at 0x1000<\/code>:<\/p>\n\n\n\n
          Mode<\/th>Syntax<\/th>Effective Address Used<\/th>Final Value of X1<\/th><\/tr><\/thead>
          Offset (Normal)<\/strong><\/td>[X1, #8]<\/code><\/td>0x1008<\/code><\/td>0x1000<\/code> (No change)<\/td><\/tr>
          Pre-Index<\/strong><\/td>[X1, #8]!<\/code><\/td>0x1008<\/code><\/td>0x1008<\/code><\/td><\/tr>
          Post-Index<\/strong><\/td>[X1], #8<\/code><\/td>0x1000<\/code><\/td>0x1008<\/code><\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n
          When to use which?<\/h3>\n\n\n\n
            \n
          1. Post-Indexing ([Xn], #offset<\/code>):<\/strong>\n
              \n
            • Most common for iterating over arrays or buffers. You process the item at the current pointer and immediately get ready for the next loop iteration by moving the pointer forward.<\/li>\n<\/ul>\n<\/li>\n\n\n\n
            • Pre-Indexing ([Xn, #offset]!<\/code>):<\/strong>\n
                \n
              • Commonly used for stack pushes<\/strong>.<\/li>\n\n\n\n
              • Example (Pushing to a Full Descending stack): You must decrement the stack pointer before<\/em> you store data, so you don’t overwrite the current top of the stack.<\/li>\n\n\n\n
              • STR X0, [SP, #-16]!<\/code> (Move SP down 16 bytes, then store X0 there).<\/li>\n<\/ul>\n<\/li>\n<\/ol>\n\n\n\n
                \n\n\n\n
                If you are looking at compiler-generated code (GCC, Clang, MSVC) or standard handwritten assembly examples, you are likely seeing Normal Offset<\/strong> addressing (e.g., str x0, [sp, #8]<\/code>) instead of Pre-indexed<\/strong> addressing (e.g., str x0, [sp, #-16]!<\/code>) for one major reason: Optimization via Fixed Stack Frames.<\/strong><\/p>\n\n\n\n
                Here is the detailed breakdown of why modern AArch64 code prefers normal offsets over pre-indexing (push-style behavior).<\/p>\n\n\n\n
                \n\n\n\n
                \n\n\n\n
                \n\n\n\n
                AArch64 Stack Operations Explained<\/h2>\n\n\n\n
                1. Breaking Dependency Chains (Performance)<\/h3>\n\n\n\n
                Modern CPUs are superscalar<\/strong> and out-of-order<\/strong>. They want to execute multiple instructions at the same time.<\/p>\n\n\n\n
                  \n
                • Pre-indexing (The “Push” approach):<\/strong>
                  If you use pre-indexing for every variable, you are modifying the Stack Pointer (sp<\/code>) in every instruction. str x0, [sp, #-16]! ; Modifies SP str x1, [sp, #-16]! ; Depends on new SP value str x2, [sp, #-16]! ; Depends on new SP value<\/code> The CPU cannot execute the second instruction until the first one finishes updating sp<\/code>. This creates a dependency chain<\/strong>, forcing the CPU to execute these instructions serially (one by one).<\/li>\n\n\n\n
                • Normal Offset (The “Frame” approach):<\/strong>
                  The compiler allocates the entire stack frame at once using a single subtraction.
                  asm sub sp, sp, #48 ; Allocate space for 3 variables (aligned) str x0, [sp, #32] ; Base address is SP, no update str x1, [sp, #16] ; Base address is SP, no update str x2, [sp, #0] ; Base address is SP, no update<\/code>
                  Since the str<\/code> instructions do not modify sp<\/code>, they are independent of each other. The CPU can execute all three stores in parallel.<\/li>\n<\/ul>\n\n\n\n
                  2. Random Access for Local Variables<\/h3>\n\n\n\n
                  In high-level languages (C, C++, Rust), the stack is not just a LIFO (Last In, First Out) queue; it is a storage area for local variables.<\/p>\n\n\n\n
                  You often need to read and write variables located in the middle of the stack frame multiple times throughout a function.<\/p>\n\n\n\n
                    \n
                  • If you used push<\/code>\/pop<\/code> logic (pre\/post-indexing), the relative offset to your variables would change constantly as sp<\/code> moves.<\/li>\n\n\n\n
                  • By allocating the frame once (sub sp, sp, #size<\/code>), sp<\/code> remains constant throughout the function body. This makes accessing variables via static offsets ([sp, #offset]<\/code>) simple and efficient.<\/li>\n<\/ul>\n\n\n\n
                    3. Addressing Range Limits<\/h3>\n\n\n\n
                    AArch64 instructions have limits on how large the immediate value (the offset) can be.<\/p>\n\n\n\n
                      \n
                    • Pre-indexed (!<\/code>) limit:<\/strong> The offset usually must fit within a narrower range (simpler encoding).<\/li>\n\n\n\n
                    • Normal Offset limit:<\/strong> The offset generally has a larger allowable range, especially when scaled.<\/li>\n<\/ul>\n\n\n\n
                      If a function has a large stack frame (e.g., a char array of 2KB), you cannot allocate it using a single pre-indexed store because the offset #-2048<\/code> might not fit in the pre-indexed encoding for that specific instruction. It is safer and more standard to sub<\/code> the sp<\/code> separately.<\/p>\n\n\n\n
                      4. The 16-Byte Alignment Requirement<\/h3>\n\n\n\n
                      The AArch64 hardware and ABI (Application Binary Interface) require the stack pointer (sp<\/code>) to be 16-byte aligned<\/strong> whenever it is used to access memory.<\/p>\n\n\n\n
                      If you were to push single 64-bit registers (8 bytes) one by one using str x0, [sp, #-8]!<\/code>, you would misalign the stack.<\/p>\n\n\n\n
                        \n
                      • To fix this, you would have to use stp<\/code> (Store Pair) to push two registers at once (stp x0, x1, [sp, #-16]!<\/code>).<\/li>\n\n\n\n
                      • However, if you have an odd number of registers to save, managing alignment via individual pushes becomes messy.<\/li>\n\n\n\n
                      • Allocating the whole frame at once (sub sp, sp, #aligned_size<\/code>) guarantees alignment is handled in one instruction.<\/li>\n<\/ul>\n\n\n\n
                        When WILL you see Pre-indexing?<\/h3>\n\n\n\n
                        You will typically see pre-indexing (and post-indexing) primarily in the Function Prologue<\/strong> and Epilogue<\/strong> for very small functions, specifically for saving the Frame Pointer (x29<\/code>) and Link Register (x30<\/code>).<\/p>\n\n\n\n
                        Common Prologue:<\/strong><\/p>\n\n\n\n
                        stp x29, x30, [sp, #-16]!  ; Pre-index: Allocate 16 bytes and save FP\/LR\nmov x29, sp                ; Set up frame pointer<\/code><\/pre>\n\n\n\n
                        Common Epilogue:<\/strong><\/p>\n\n\n\n
                        ldp x29, x30, [sp], #16    ; Post-index: Restore FP\/LR and deallocate 16 bytes\nret<\/code><\/pre>\n\n\n\n
                        But for the rest of the function code?<\/strong> It will almost exclusively be Normal Offsets.<\/p>\n","protected":false},"excerpt":{"rendered":"
                        In AArch64 (ARMv8-A 64-bit architecture), Pre-indexing and Post-indexing are memory […]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[42],"tags":[13,30],"class_list":["post-269","post","type-post","status-publish","format-standard","hentry","category-knowledge-base","tag-aarch64","tag-binary"],"_links":{"self":[{"href":"https:\/\/haco.club\/index.php?rest_route=\/wp\/v2\/posts\/269","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/haco.club\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/haco.club\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/haco.club\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/haco.club\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=269"}],"version-history":[{"count":3,"href":"https:\/\/haco.club\/index.php?rest_route=\/wp\/v2\/posts\/269\/revisions"}],"predecessor-version":[{"id":272,"href":"https:\/\/haco.club\/index.php?rest_route=\/wp\/v2\/posts\/269\/revisions\/272"}],"wp:attachment":[{"href":"https:\/\/haco.club\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=269"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/haco.club\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=269"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/haco.club\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=269"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}